The importance of keeping parasitic capacitances low in MOS transistors has long been recognized and the industry has expended considerable effort in developing fabrication processes which result in transistors with low values of parasitic capacitances.
There are two major possible sources of parasitic capacitances in an MOS transistor. One is the overlap of the gate electrode over the edges of the source and drain regions. This overlap typically is controlled by processes which use the gate region (electrode) as the implantation mask for controlling the critical edge of the ion-implanted regions formed for the source and drain. Such processes are generally described as self-aligned processes.
The other possible major source of parasitic capacitance is associated with the interface or junction between the localized source and drain regions and the silicon substrate in which they are formed. To control this source, it is known to form the source and drain regions in a semiconductive layer which has been formed on an insulating substrate. Such silicon-on-insulator structures tend to be expensive to make and to have operating problems, such as kink-effects, and so have had limited acceptance. Alternatives to such a structure include structures in which buried dielectric regions of either silicon oxide or silicon nitride extend partially around the source and drain regions to limit the parasitic capacitance of such regions. These fabrication processes also tend to be complex, particularly if adapted to utilize self-aligned source and drain regions.
One example of a silicon-on-insulator like transistor is the "mushroom" shaped Field Effect Transistor (FET) shown in Eupopean Patent Application No. 81104511.1, filed Nov. 6, 1981. The "mushroom" shape is essentially a relatively narrow "stem" of silicon grown through an oxide layer and having a silicon "head", of larger lateral dimension than the "stem", grown on top of the oxide layer. When the "mushroom" shape is formed by growing silicon, first vertically and then laterally over a step in an oxide layer, the silicon grown over the step has a tendency to become polycrystalline. Field Effect Transistors (FETs) having polycrystalline channel regions typically have poorer performance than those with monocrystalline (single) silicon channel regions. The FETs can be Insulated Gate Field Effect Transistors (IGFETs) of the Metal-Oxide-Silicon (MOS) type or Junction Field Effect Transistors (J-FETs).
A buried insulating layer can be used to make a silicon-on-insulator like transistor structure. This is done by implantation of suitable ions, such as of oxygen or nitrogen, to convert the implanted region to an insulating silicon compound. Such techniques are difficult and do not yet appear to be commercially successful.
It would be desirable to have an economically viable process for producing a silicon-on-insulator like transistor structure which has relatively low drain and source to semiconductor body (substrate) capacitance and has an essentially monocrystalline silicon channel region that provides the performance of conventional transistor structures.